FIG. 1 is an illustration of an exemplary conventional eight transistor (8T) dual-port Static Random Access Memory (SRAM) circuit 100. The SRAM circuit 100 includes the memory cell 101, which is made of back-to-back inverters. The data value in the memory cell 101 is stored at node 102, and the inverse of the data value is stored at node 103. The SRAM circuit 100 includes two data-in lines DINa and DINb, which are in communication with respective data sources, for example multiple microprocessors. The data-in line DINa is in communication with the bit lines a_bit and a_bitb (“bit line a bar”). Similarly, the data-in line DINb is in communication with the bit lines b_bit and b_bitb (“bit line b bar”). The bit lines a_bit and a_bitb are enabled by the pass-gates 109, 111, and the bit lines b_bit and b_bitb are enabled by the pass-gates 108, 110.
The SRAM circuit 100 includes two word lines, a_wl and b_wl, corresponding to respective data sources. Word line a_wl is coupled to the memory cell 101 through pass-gates 106, 107, and the word line b_wl is coupled to the memory cell 101 through the pass-gates 104, 105.
To avoid a scenario wherein both data sources write different values to the memory element 101 at the same time, higher level logic (not shown) only allows a single write operation from one of the data sources to the circuit 100 to be performed at any given time. However, two substantially simultaneous read operations may be performed on the circuit 100 to facilitate multiple-core designs.
One problem with dual port SRAM circuits (such as the circuit 100) is that the design has double pass-gates (e.g., pass-gates 104-107) on either side of the memory cell. When a dual read operation is performed, the pass-gates 104-107 are on, and two of the bit lines are at high voltage, VDD. In the dual read operation, the high voltage of the bit lines can cause double disturbance to the cell compared to 6T designs that have only a single pass-gate on each side of the memory cell. More disturbance can lead to less stability in the example of FIG. 1, by causing values to “flip” incorrectly during dual read operations.
The relative strengths of the P-type Field Effect Transistors (PFETs) and N-type Field Effect Transistors (NFETs) in the memory cell are selected so as to give a reasonable read margin, as measured by Signal Noise Margin (SNM). However, the benefits to the read margin come at the expense of the write margin. That is, an increased read margin results in a decreased write margin (and vice versa). Thus, the selected relative strengths of the PFETs and NFETs in the memory cell may increase the difficulty of writing. The effect on the write margin is notable because, in a single write operation, data is written using only a single pass-gate on each side of the memory cell, e.g., pass-gates 106 and 107 to write from DINa. Accordingly, when the write margin is low, write speed can be somewhat slow for the circuit of FIG. 1.